1. Field of the Invention
The present invention relates to an optical communication interface module connected to an electrical communication interface module of inter-integrated circuit (to be abbreviated as I2C hereinafter) communication protocol, and more particularly, to an optical communication interface module connected to a direct-current (DC) power terminal, an input/output (I/O) terminal and a ground terminal of an electric communication interface module of I2C communication protocol, to perform optical communication. Here, the I/O terminal refers to an I/O terminal to/from which a serial data signal or a serial clock signal of the I2C communication protocol is input/output.
2. Description of the Related Art
FIG. 1 shows waveforms for explaining an I2C communication protocol.
Referring to FIG. 1, the I2C communication protocol is a protocol for performing serial communication by only two channels for a serial data signal SDA and a serial clock signal SCL, without a channel for a control signal, unlike in a typical serial communication protocol. According to the I2C communication protocol, whenever the serial clock signal SCL becomes a logic state of ‘1’ (a higher voltage level VH), the state of the serial data signal SDA is set.
A time t1 at which the serial data signal SDA falls from a logic value of ‘1’ to a logic value of ‘0’ (a lower voltage level VL), while the serial clock signal SCL has a logic value of ‘1’, is a starting time of a data packet. A time t14 at which the serial data signal SDA rises from a logic value of ‘0’ to a logic value of ‘1’ while the serial clock signal SCL has a logic value of ‘1’, is a terminating time of a data packet. Thus, in the time period of t1–t14 for a data packet, the serial data signal SDA must not undergo logic transition while the corresponding serial clock signal SCL.
Data having a logic value of ‘1’, are sequentially transmitted or received for the duration of t2–t3 in which the serial clock signal SCL has a logic value of ‘1’, data having a logic value of ‘0’ for the duration of t4–t5, data having a logic value of ‘1’ for the duration of t10–t11, and data having a logic value of ‘1’ for the duration of t12–t13, respectively.
FIG. 2 shows general electric communication interface modules of I2C communication protocol, which are modules for a serial data signal SDA, and are the same as those for a serial clock signal SCL. In FIG. 2, reference mark SDA1IN denotes a serial data input signal supplied from a first module El1, SDA1OUT a serial data output signal supplied from the first module El1, SDA2IN a serial data input signal supplied from a second module El2, and SDA2OUT a serial data input signal supplied from the second module El2, respectively.
A procedure in which the serial data output signal SDA1OUT in the first module El1 is transmitted from the first module El1 and received at the second module El2, will now be described with reference to FIG. 2.
If the first serial output data SDA1OUT is at a logic ‘1’ level, a first transistor TR1 is turned ON. Accordingly, a current flows from a second power terminal VCC2 of the second module El2 to a ground terminal via a pull-up resistor Rp2, a second terminal P2, an electric current line CL, the first transistor TR1 and a first current source CS1. Thus, the potential of a second terminal P2 is decreased, so that the second serial data input signal SDA2IN received through an inverter B2 of the second module El2 becomes at a logic ‘1’ level, that is, the current flows in a direction indicated by D1.
Conversely, if the first serial output data SDA1OUT is at a logic ‘0’ level, the first transistor TR1 is turned OFF. Accordingly, the potentials of the first and second terminals P1 and P2 are increased, so that the second serial data input signal SDA2IN received through the inverter B2 of the second module El2 becomes at logic ‘0’ level.
The above-described transmission/reception procedure is the same as a procedure in which the serial data output signal SDA2OUT in the second module El2 is transmitted from the second module El2 and received at the first module El1. The transmission/reception procedure of the serial clock signal SCL is also the same as described above.
According to the conventional electric communication interface module, the communication speed is reduced due to the internal resistance of the current line CL itself and the maximum communication path becomes shorter.